The present invention is directed generally to testing digital apparatus such as is found in data processing systems. The invention relates more particularly to test techniques in which sequences of pseudo-random test patterns are shifted ("scanned") into and out of digital apparatus, producing resultant signatures from which can be determined whether or not the apparatus under test will function without fault. In particular, the invention provides a method, and apparatus implementing that method, for functionally scan testing a digital system of the type including a bus structure that is accessible by individual units on a mutually exclusive basis.
The advent of large scale and very large scale integration (LSI and VLSI) produced a variety of techniques for testing the very large amounts of digital circuitry that can found in integrated circuits (ICs) and combinations of ICs (e.g., as may be found on printed circuit or other types of boards and systems). One such technique involves application of a variety of known test signals to the IC or combination of ICs (hereinafter "digital system") and observing the output signals produced in response to determine if what was expected was produced by the digital system. An offshoot of this approach, and one that is becoming increasingly popular, involves designing the elemental memory stages of the system (i.e., single bit storage such as flip flops, latches, and the like) to be capable of functioning in one of two modes: a first or "run" mode in which the memory stage operates in its capacity for which it was incorporated in the digital system (e.g., a component of the system, operating to receive, store, and pass on system information bits in response to normal logic system control signals); and a second or "scan" mode in which a number of the memory stages are intercoupled in series to form one or more extended shift registers or, as more commonly referred to in the art, "scan strings" or "scan chains."
One method of using these scan strings involves forming known test patterns ("vectors") that are put in place in the digital system by shifting ("scanning") them into the system using the scan chains. The system is then allowed to run for a period of time (e.g., one or more clock periods), and the state of the system (i.e., the content of each memory stage) removed for observation, again using the scan chains.
There are a number of variations on this approach, one of which involves using the scan chains to place the digital system in a pseudo-random state to test the operability of the system. According to this approach, the system is switched from the first or run mode to the scan mode for receiving pseudo-random bit patterns that are scanned into the scan strings to place the system in a pseudo-random state. The technique may include the step of returning the system momentarily to its run mode configuration, and permitting it to operate for one clock cycle. The system is then returned to the scan mode, the digital state (i.e., the content of the scan string or strings) extracted (again by scanning), and that state then analyzed to determine the operability of the stages and interconnections of the system, and thereby the system itself.
Preferably, the steps of configuring the system to form the scan chains, scanning in the pseudo-random data, reinstating the normal configuration for an execution cycle, and returning the system to a scan configuration to remove (scan out) the resultant (pseudo-random) state is repeatedly performed with the extracted state compressed (such as through a cyclic redundancy) to form a "signature" that can be compared to a known, defect-free signature. If the signatures match, the test is considered to have been passed. This testing technique is usually referred to as "pseudo-random scan testing."
Among the underlying principles of pseudo-random scan test methods is that the test must be repeatable or "deterministic" in the sense that each time a digital system is tested, the results of that test will be the same if the system is without fault. Examples of such pseudo-random test methods and apparatus may be found in U.S. Pat. Nos. 4,718,065, 4,534,028, and 4,827,476.
Pseudo-random scan testing can provide many benefits. It is a cost effective test method that can be performed without the need to form special test vectors in advance; it can be performed very fast to check or verify the operability of very large amounts of digital circuitry; and it can be performed using test circuitry less expensive and less complex than other test techniques. However, pseudo-random testing is not without certain problems.
One such problem is the obvious difficulty, if not inability, to predict in advance the state that the test signals will take on during the test period. Circuitry contained in the digital system that may produce different results (e.g., random access memory units, inputs from external sources, etc.) from test to test must either be excluded from testing or somehow designed so that, during pseudo-random testing, it will produce deterministic results.
This problem has been particularly troublesome in digital systems incorporating a bus structure that is shared (e.g., a three-state bus structure) on a mutually exclusive basis by two or more digital subsystems to communicate data therebetween. When such a system is subjected to pseudo-random testing, there exists the possibility that, at any moment in time, two or more of the subsystems will be attempting to drive data onto the data bus at the same time. The moment may see the bus assuming one state in one test (or portion of test), and assuming another state in another test. Since it is not entirely certain what state the bus will assume from test to test, the test can no longer be termed deterministic. Perhaps more importantly, the bus may be damaged by being driven by two or more of the subsystems at the same time.
A flip side to the forgoing problem involves the situation of none of the subsystems driving the shared bus, allowing it to float. In this case the bus can assume a non-deterministic value, which one or more of the subsystems will attempt to read so that, again from test to test, different test results can be produced.
One approach to solving this problem has been to include in the system a bus arbiter that receives requests for access to the bus. Using decoder circuitry, the arbiter issues a mutually exclusive bus enable signal to one and only one requester. This approach permits pseudo-random testing since the arbiter circuitry cannot permit more than one subsystem to drive the bus at any one moment in time. However, the approach tends to limit normal operating performance due to the extra time it takes to perform the arbitration. Thus, digital systems with such shared bus configurations have usually taken the approach of locking out the circuitry that drives the bus during pseudo-random testing, and the bus itself. This has resulted in the system not being completely tested--if tested at all.
Accordingly, there is a need for including in pseudo-random scan testing techniques a methodology and apparatus that can permit the test to include the shared bus and the circuitry used to access that bus.